Class AXI_RO_rtl

TSSV Interface bundle for the AXI_RO_rtl protocol

Hierarchy (view full)

Interface
- AXI_RO_rtl

Index

Constructors

Properties

params VLNV name signals role? modports?

Methods

interfaceName writeSystemVerilog

Constructors

constructor

new AXI_RO_rtl(params?, role?): AXI_RO_rtl
Create a new AXI_RO_rtl Interface bundle with either master or slave port interface or just a bundle of interconnect wires
Parameters
- Optional params: AXI_RO_rtl_Parameters
  param value set
- Optional role: AXI_RO_rtl_Role
  sets the role of this instance to choose master or slave port interface or just a bundle of interconnect wires
Returns AXI_RO_rtl
Overrides Interface.constructor
- Defined in out/src/interfaces/AMBA/AMBA3/AXI_RO/r2p0_0/AXI_RO_rtl.d.ts:51

Properties

params

params: AXI_RO_rtl_Parameters

`Static` `Readonly` VLNV

VLNV: {
    vendor: string;
    library: string;
    name: string;
    version: string;
}

VLNV Metadata

Type declaration

vendor: string
library: string
name: string
version: string

name

name: string

signals

signals: Signals

`Optional` role

role?: string

`Optional` modports

modports?: Record<string, Record<string, PortDirection>>

Methods

interfaceName

interfaceName(): string
Returns string
Inherited from Interface.interfaceName
- Defined in ts/src/core/Base.ts:157

writeSystemVerilog

writeSystemVerilog(): string
Returns string
Inherited from Interface.writeSystemVerilog
- Defined in ts/src/core/Base.ts:162

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