Class AXI4XBar

The Module class is the base class for all TSSV modules.

Hierarchy (view full)

Module
- AXI4XBar

Constructors

constructor

new AXI4XBar(params): AXI4XBar
Parameters
- params: AXI4XBarParams
Returns AXI4XBar
Overrides Module.constructor
- Defined in ts/src/modules/AXI4XBar.ts:49

Properties

`Readonly` name

name: string

name contains the resulting SystemVerilog module name

`Protected` signals

signals: Signals

`Protected` submodules

submodules: Record<string, {
module: Module;
bindings: Record<string, string | bigint | Sig>;
}>

Type declaration

module: Module
bindings: Record<string, string | bigint | Sig>

`Protected` bindingRules

bindingRules: {
    input: string[];
    output: string[];
    inout: string[];
} = ...

Type declaration

input: string[]
output: string[]
inout: string[]

`Protected` body

body: string

`Protected` registerBlocks

registerBlocks: Record<string, Record<string, Record<string, Record<string, {
d: string;
resetVal?: bigint;
}>>>> = {}

`Static` `Protected` printedInterfaces

printedInterfaces: Record<string, boolean> = {}

`Protected` verilogParams

verilogParams: Record<string, boolean>

Methods

setVerilogParameter

setVerilogParameter(param): void
Parameters
- param: string
Returns void
Inherited from Module.setVerilogParameter
- Defined in ts/src/core/Base.ts:260

addInterface

addInterface(instanceName, _interface): Interface
adds an interface signal bundle
Parameters
- instanceName: string
  the name for this instance of the signal bundle
- _interface: Interface
  the type of interface to add
Returns Interface
the resulting interface for connecting to modules and add* primitives
Inherited from Module.addInterface
- Defined in ts/src/core/Base.ts:285

addSubmodule

addSubmodule(instanceName, submodule, bindings, autoBind?, createMissing?, autoWidthExtension?): Module
instantiate another module a a submodule
Parameters
- instanceName: string
  sets the instance mane
- submodule: Module
  the module to instantiate
- bindings: Record<string, string | bigint | Sig>
  define the connections of the submodule
- autoBind: boolean = true
  find signals in parent with matching name for signals that are not explicitly bound
- createMissing: boolean = false
- autoWidthExtension: boolean = false
Returns Module
returns the resulting submodule instance
Inherited from Module.addSubmodule
- Defined in ts/src/core/Base.ts:301

addSystemVerilogSubmodule

addSystemVerilogSubmodule(instanceName, SVFilePath, params, bindings, autoBind?): Module
Parameters
- instanceName: string
- SVFilePath: string
- params: TSSVParameters
- bindings: Record<string, string | Sig>
- autoBind: boolean = true
Returns Module
Inherited from Module.addSystemVerilogSubmodule
- Defined in ts/src/core/Base.ts:428

`Protected` simpleHash

simpleHash(str): string
Parameters
- str: string
Returns string
Inherited from Module.simpleHash
- Defined in ts/src/core/Base.ts:460

`Protected` bigintToSigName

bigintToSigName(value, isSigned?, width?): string
Parameters
- value: bigint
- Optional isSigned: boolean
- Optional width: number
Returns string
Inherited from Module.bigintToSigName
- Defined in ts/src/core/Base.ts:470

`Protected` findSignal

findSignal(sig, throwOnFalse?, caller?, throwOnArray?): IOSignal | Signal
Parameters
- sig: string | bigint | Sig
- throwOnFalse: boolean = false
- caller: null | string | ((...args) => any) = null
- Optional throwOnArray: boolean
Returns IOSignal | Signal
Inherited from Module.findSignal
- Defined in ts/src/core/Base.ts:487

addSignal

addSignal(name, signal): Sig
add a signal to the SystemVerilog module
Parameters
- name: string
  name of the signal
- signal: Signal
  parameters of the signal
Returns Sig
signal that can be passed to other add* functions to make connections
Inherited from Module.addSignal
- Defined in ts/src/core/Base.ts:534

addRegister

addRegister(io): Sig
add a DFF register(can be multi-bit) to the d input
Parameters
- io: {
      d: string | Sig | Expr;
      clk: string | Sig;
      reset?: string | Sig;
      resetVal?: bigint;
      en?: string | Sig | Expr;
      q?: string | Sig;
  }
  the input/output of the register
  - d: string | Sig | Expr
  - clk: string | Sig
  - Optional reset?: string | Sig
  - Optional resetVal?: bigint
  - Optional en?: string | Sig | Expr
  - Optional q?: string | Sig
Returns Sig
return the q output signal
Inherited from Module.addRegister
- Defined in ts/src/core/Base.ts:545

bitWidth

bitWidth(a, isSigned?): number
get the number of bits need to represent an integer value
Parameters
- a: number | bigint
  the value to determine the bit width of
- isSigned: boolean = false
  whether the value should be treated as a signed number
Returns number
the minimum bit width needed to represent the value
Inherited from Module.bitWidth
- Defined in ts/src/core/Base.ts:635

addRound

addRound(io, roundMode?): Sig
add a rounding operation to scale down and reduce the bit width of a signal
Parameters
- io: {
      in: string | Sig;
      out: string | Sig;
      rShift: string | number | Sig;
  }
  the input/output signals of the round operation the rShift signal determines the number of LSBs to round away. The rShift signal can be either a liternal constant or a variable shift. When using a variable shift, care should be taken to minimize the number of bits to minimize the impact on the timing path of the resulting logic.
  - in: string | Sig
  - out: string | Sig
  - rShift: string | number | Sig
- roundMode: "rp" | "rm" | "rz" | "rn" | "rna" = 'rp'
  determines the type of rounding to apply
Returns Sig
the signal of the rounded result
Inherited from Module.addRound
- Defined in ts/src/core/Base.ts:648

addSaturate

addSaturate(io, satMode?): Sig
add a Saturate operation to limit the bit width of a signal without overflow
Parameters
- io: {
  in: string | Sig;
  out: string | Sig;
  }
  the input and output signals of the saturation operation
  - in: string | Sig
  - out: string | Sig
- satMode: "balanced" | "none" | "simple" = 'simple'
  determines the behavior of the saturation
Returns Sig
signal of the result of the saturation
Inherited from Module.addSaturate
- Defined in ts/src/core/Base.ts:686

addSequentialAlways

addSequentialAlways(io, body): void
Parameters
- io: {
      clk: string | Sig;
      reset?: string | Sig;
      outputs: (string | Sig)[];
  }
  - clk: string | Sig
  - Optional reset?: string | Sig
  - outputs: (string | Sig)[]
- body: string
Returns void
Inherited from Module.addSequentialAlways
- Defined in ts/src/core/Base.ts:739

addCombAlways

addCombAlways(io, body): void
Parameters
- io: {
  inputs?: (string | Sig)[];
  outputs: (string | Sig)[];
  }
  - Optional inputs?: (string | Sig)[]
  - outputs: (string | Sig)[]
- body: string
Returns void
Inherited from Module.addCombAlways
- Defined in ts/src/core/Base.ts:792

addLatchAlways

addLatchAlways(io, body): void
Parameters
- io: {
  inputs?: (string | Sig)[];
  outputs: (string | Sig)[];
  }
  - Optional inputs?: (string | Sig)[]
  - outputs: (string | Sig)[]
- body: string
Returns void
Inherited from Module.addLatchAlways
- Defined in ts/src/core/Base.ts:836

`Protected` addOperation

addOperation(op, io): Sig
Parameters
- op: BinaryOp
- io: OperationIO
Returns Sig
Inherited from Module.addOperation
- Defined in ts/src/core/Base.ts:880

addMultiplier

addMultiplier(io): Sig
Parameters
- io: OperationIO
Returns Sig
Inherited from Module.addMultiplier
- Defined in ts/src/core/Base.ts:982

addAdder

addAdder(io): Sig
adds an arithmetic adder to the generated SystemVerilog module
Parameters
- io: OperationIO
  the input/output interface of the adder
Returns Sig
the sum result
Inherited from Module.addAdder
- Defined in ts/src/core/Base.ts:991

addSubtractor

addSubtractor(io): Sig
adds an arithemetic subtractor to the generated SystemVerilog module
Parameters
- io: OperationIO
  the input/output interface of the subtractor
Returns Sig
the difference result
Inherited from Module.addSubtractor
- Defined in ts/src/core/Base.ts:1000

addConstSignal

addConstSignal(name, value, isSigned?, width?): Sig
add a constant literal signal to the generated SystemVerilog module
Parameters
- name: undefined | string
  signal name
- value: bigint
  signal literal value
- isSigned: boolean = false
  whether the signal is signed or not
- width: undefined | number = undefined
  bit width of the resulting signal
Returns Sig
Inherited from Module.addConstSignal
- Defined in ts/src/core/Base.ts:1012

addConstSignals

addConstSignals(name, values, isSigned?, width?): Sig[]
add an array of constant literal signals to the generated SystemVerilog module
Parameters
- name: string
  signal name
- values: bigint[]
  the literal values of the array
- isSigned: boolean = false
  whether the signals are signed or not
- width: undefined | number = undefined
  bit width of the resulting signals
Returns Sig[]
The array of signals
Inherited from Module.addConstSignals
- Defined in ts/src/core/Base.ts:1034

addAssign

addAssign(io): Sig
add a SystemVerilog continuous assign statement
Parameters
- io: {
  in: Expr;
  out: string | Sig;
  }
  expression that is the right hand side of the assigment
  - in: Expr
  - out: string | Sig
Returns Sig
signal that is the left hand side of the assignment
Inherited from Module.addAssign
- Defined in ts/src/core/Base.ts:1048

addMux

addMux(io): Sig
add a multiplexer to the TSSV module
Parameters
- io: {
      in: (string | Sig | Expr)[];
      sel: string | Sig | Expr;
      out: string | Sig;
      default?: string | Sig | Expr;
  }
  The input/output signals connected to the multiplexer
  - in: (string | Sig | Expr)[]
  - sel: string | Sig | Expr
  - out: string | Sig
  - Optional default?: string | Sig | Expr
Returns Sig
signal of the multiplexer output
Inherited from Module.addMux
- Defined in ts/src/core/Base.ts:1065

debug

debug(): void
print some debug information to the console

Returns void
Inherited from Module.debug
- Defined in ts/src/core/Base.ts:1114

writeSystemVerilog

writeSystemVerilog(): string
write the generated SystemVerilog code to a string

Returns string
string containing the generated SystemVerilog code for this module
Inherited from Module.writeSystemVerilog
- Defined in ts/src/core/Base.ts:1127

Class AXI4XBar

Hierarchy (view full)

Index

Constructors

Properties

Methods

Constructors

constructor

Parameters

Returns AXI4XBar

Properties

Readonly name

Protected signals

Protected submodules

Type declaration

module: Module

bindings: Record<string, string | bigint | Sig>

Protected bindingRules

Type declaration

input: string[]

output: string[]

inout: string[]

Protected body

Protected registerBlocks

Static Protected printedInterfaces

Protected verilogParams

params

IOs

interfaces

Methods

setVerilogParameter

Parameters

Returns void

addInterface

Parameters

Returns Interface

addSubmodule

Parameters

Returns Module

addSystemVerilogSubmodule

Parameters

Returns Module

Protected simpleHash

Parameters

Returns string

Protected bigintToSigName

Parameters

Returns string

Protected findSignal

Parameters

Returns IOSignal | Signal

addSignal

Parameters

Returns Sig

addRegister

Parameters

d: string | Sig | Expr

clk: string | Sig

Optional reset?: string | Sig

Optional resetVal?: bigint

Optional en?: string | Sig | Expr

Optional q?: string | Sig

Returns Sig

bitWidth

Parameters

Returns number

addRound

Parameters

in: string | Sig

out: string | Sig

rShift: string | number | Sig

Returns Sig

addSaturate

Parameters

in: string | Sig

out: string | Sig

Returns Sig

addSequentialAlways

Parameters

clk: string | Sig

`Readonly` name

`Protected` signals

`Protected` submodules

`Protected` bindingRules

`Protected` body

`Protected` registerBlocks

`Static` `Protected` printedInterfaces

`Protected` verilogParams

`Protected` simpleHash

`Protected` bigintToSigName

`Protected` findSignal

`Optional` reset?: string | Sig

`Optional` resetVal?: bigint

`Optional` en?: string | Sig | Expr

`Optional` q?: string | Sig

`Optional` reset?: string | Sig

`Optional` inputs?: (string | Sig)[]

`Optional` inputs?: (string | Sig)[]

`Protected` addOperation

`Optional` default?: string | Sig | Expr