Class Memory

Interface is a class to define a signal bundle for a standardized interface. It wraps the modport functionality of an SV interface allowing different port views of the signal bundle as well as just a bundle of wires. Interfaces simpilfy interface signal binding by combining all signals into a single bundled bind.

Hierarchy (view full)

Constructors

constructor

Properties

name role? modports? params signals

Methods

interfaceName writeSystemVerilog

Constructors

constructor

Properties

name

name: string

Optional role

role?: string

Optional modports

modports?: Record<string, Record<string, PortDirection>>

params

params: Memory_Parameters

signals

signals: {
    ADDR: {
        width: 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64;
    };
    DATA_WR: {
        width: 32 | 64 | 128 | 256 | 512 | 1024;
    };
    DATA_RD: {
        width: 32 | 64 | 128 | 256 | 512 | 1024;
    };
    RE: {
        width: number;
    };
    WE: {
        width: number;
    };
    READY: {
        width: number;
    };
    WSTRB: {
        width: number;
    };
}

Type declaration

  • ADDR: {
        width: 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64;
    }
    • width: 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64
  • DATA_WR: {
        width: 32 | 64 | 128 | 256 | 512 | 1024;
    }
    • width: 32 | 64 | 128 | 256 | 512 | 1024
  • DATA_RD: {
        width: 32 | 64 | 128 | 256 | 512 | 1024;
    }
    • width: 32 | 64 | 128 | 256 | 512 | 1024
  • RE: {
        width: number;
    }
    • width: number
  • WE: {
        width: number;
    }
    • width: number
  • READY: {
        width: number;
    }
    • width: number
  • WSTRB: {
        width: number;
    }
    • width: number

Methods

interfaceName

writeSystemVerilog

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