Class AXI5_rtl

TSSV Interface bundle for the AXI5_rtl protocol

Hierarchy (view full)

Interface
- AXI5_rtl

Index

Constructors

Properties

name signals role? modports? params VLNV

Methods

interfaceName writeSystemVerilog

Constructors

constructor

new AXI5_rtl(params?, role?): AXI5_rtl
Create a new AXI5_rtl Interface bundle with either master or slave port interface or just a bundle of interconnect wires
Parameters
- params: AXI5_rtl_Parameters = {}
  param value set
- role: AXI5_rtl_Role = undefined
  sets the role of this instance to choose master or slave port interface or just a bundle of interconnect wires
Returns AXI5_rtl
Overrides Interface.constructor
- Defined in ts/src/interfaces/AMBA/AMBA5/AXI5/r0p0_0/AXI5_rtl.ts:55

Properties

name

name: string

signals

signals: Signals

`Optional` role

role?: string

`Optional` modports

modports?: Record<string, Record<string, PortDirection>>

params

params: AXI5_rtl_Parameters

`Static` `Readonly` VLNV

VLNV: {
    vendor: string;
    library: string;
    name: string;
    version: string;
} = ...

VLNV Metadata

Type declaration

vendor: string
library: string
name: string
version: string

Methods

interfaceName

interfaceName(): string
Returns string
Inherited from Interface.interfaceName
- Defined in ts/src/core/Base.ts:157

writeSystemVerilog

writeSystemVerilog(): string
Returns string
Inherited from Interface.writeSystemVerilog
- Defined in ts/src/core/Base.ts:162

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